RESUMO
This study proposed a novel source/drain (S/D) extension scheme to increase the stress in nanosheet (NS) field-effect transistors (NSFETs) and investigated the scheme by using technology-computer-aided-design simulations. In three-dimensional integrated circuits, transistors in the bottom tier were exposed to subsequent processes; therefore, selective annealing, such as laser-spike annealing (LSA), should be applied. However, the application of the LSA process to NSFETs significantly decreased the on-state current (Ion) owing to diffusionless S/D dopants. Furthermore, the barrier height below the inner spacer was not lowered even under on-state bias conditions because ultra-shallow junctions between the NS and S/D were formed far from the gate metal. However, the proposed S/D extension scheme overcame these Ion reduction issues by adding an NS-channel-etching process before S/D formation. A larger S/D volume induced a larger stress in the NS channels; thus, the stress was boosted by over 25%. Additionally, an increase in carrier concentrations in the NS channels improved Ion. Therefore, Ion increased by approximately 21.7% (37.4%) in NFETs (PFETs) compared with NSFETs without the proposed scheme. Additionally, the RC delay was improved by 2.03% (9.27%) in NFETs (PFETs) compared with NSFETs using rapid thermal annealing. Therefore, the S/D extension scheme overcame the Ion reduction issues encountered in LSA and significantly enhanced the AC/DC performance.
RESUMO
In this study, the electrical properties of Al2O3 film were analyzed and optimized to improve the properties of the passivation layer of CMOS image sensors (CISs). During Al2O3 deposition processing, the O2 plasma exposure time was adjusted, and H2 plasma treatment as well as post-metallization annealing (PMA) were performed as posttreatments. The flat-band voltage (Vfb) was significantly shifted (ΔVfb = 2.54 V) in the case of the Al2O3 film with a shorter O2 plasma exposure time; however, with a longer O2 plasma exposure time, Vfb was slightly shifted (ΔVfb = 0.61 V) owing to the reduction in the carbon impurity content. Additionally, the as-deposited Al2O3 sample with a shorter O2 plasma exposure time had a larger number of interface traps (interface trap density, Dit = 8.98 × 1013 eV-1·cm-2). However, Dit was reduced to 1.12 × 1012 eV-1·cm-2 by increasing the O2 plasma exposure time and further reduced after PMA. Consequently, we fabricated an Al2O3 film suitable for application as a CIS passivation layer with a reduced number of interface traps. However, the Al2O3 film with increased O2 plasma exposure time deteriorated owing to plasma damage after H2 plasma treatment, which is a method of reducing carbon impurity content. This deterioration was validated using the C-V hump and breakdown characteristics.
RESUMO
In this paper, we investigated TiO2 as gate dielectric to achieve the large dielectric constant. The ultra high-k value over 30 was obtained by Capacitance-Voltage measurement of Al/Ti/TiO2/Si Metal-Insulator-Semiconductor (MIS) capacitor. Among as deposited, rapid thermal annealing (RTA) at 750 °C and 1000 °C, the RTA at 750 °C showed the lowest gate leakage current. It implies that TiO2 has optimum RTA temperature having the lowest leakage current. When TiO2 is annealed at 750 °C, the phase of TiO2 changes to anatase and interfacial layer between TiOx and Si was formed. While TiO2 is annealed at 1000 °C, the phase of TiO2 changes to rutile and diffusion of silicon atoms was clearly observed and it causes the silicide formation. Based on measurement data, we proposed the energy band diagram of Al/TiO2/Si MIS capacitors. This diagram shows that the energy band gap of RTA at 750 °C is expanded while that of RTA at 1000 °C is contracted. In addition, TiO2 with RTA at 550 °C was tested to confirm leakage current and it shows lower leakage current than RTA at 750 °C as we expected. This result confirmed that optimum RTA temperature of TiO2 would exist under 750 °C.
